one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a picoampere input current bipolar op amp ad705 features dc performance 25 m v max offset voltage (ad705t) 0.6 m v/ 8 c max drift (ad705k/t) 100 pa max input bias current (ad705k) 600 pa max i b over mil temperature range (ad705t) 114 db min cmrr (ad705k/t) 114 db min psrr (ad705t) 200 v/mv min open loop gain 0.5 m v p-p typ noise, 0.1 hz to 10 hz 600 m a max supply current ac performance 0.15 v/ m s slew rate 800 khz unity gain crossover frequency 10,000 pf capacitive load drive capability low cost available in 8-pin plastic mini-dlp, hermetic cerdip and surface mount (soic) packages mil-std-883b processing available dual version available: ad706 quad version: ad704 applications low frequency active filters precision instrumentation precision integrators connection diagram plastic mini-dip (n) cerdip (q) and plastic soic (r) packages product description the ad705 is a low power bipolar op amp that has the low in- put bias current of a bifet amplifier but which offers a signifi- cantly lower i b drift over temperature. the ad705 offers many of the advantages of bifet and bipolar op amps without their inherent disadvantages. it utilizes superbeta bipolar input tran- sistors to achieve the picoampere input bias current levels of fet input amplifiers (at room temperature), while its i b typi- cally only increases 5 times vs. bifet amplifiers which exhibit a 1000x increase over temperature. this means that, at room temperature, while a typical bifet may have less i b than the ad705, the bifets input current will increase to a level of several na at +125 c. superbeta bipolar technology also per- mits the ad705 to achieve the microvolt offset voltage and low noise characteristics of a precision bipolar input amplifier. the ad705 is a high quality replacement for the industry- standard op07 amplifier while drawing only one sixth of its power supply current. since it has only 1/20th the input bias current of an op07, the ad705 can be used with much higher source impedances, while providing the same level of dc preci- sion. in addition, since the input bias currents are at picoamp levels, the commonly used balancing resistor (connected be- tween the noninverting input of a bipolar op amp and ground) is not required. the ad705 is an excellent choice for use in low frequency ac- tive filters in 12- and 14-bit data acquisition systems, in preci- sion instrumentation and as a high quality integrator. the ad705 is internally compensated for unity gain and is available in five performance grades. the ad705j and ad705k are rated over the commercial temperature range of 0 c to +70 c. the ad705a and ad705b are rated over the industrial temperature range of C40 c to +85 c. the ad705t is rated over the military temperature range of C55 c to +125 c and is available processed to mil-std-883b, rev. c. the ad705 is offered in three varieties of 8-pin package: plastic dip, hermetic cerdip and surface mount (soic). j grade chips are also available. product highlights 1. the ad705 is a low drift op amp that offers bifet level input bias currents, yet has the low i b drift of a bipolar ampli- fier. it upgrades the performance of circuits using op amps such as the lt1012. 2. the combination of analog devices advanced superbeta processing technology and factory trimming provides both low drift and high dc precision. 3. the ad705 can be used in applications where a chopper am- plifier would normally be required but without the choppers inherent noise and other problems. offset null ?n +in v offset null v+ output over comp 1 2 3 4 8 7 6 5 top view ad705
ad705Cspecifications ad705j/a ad705k/b ad705t parameter conditions min typ max min typ max min typ max units input offset voltage initial offset 30 90 10 35 10 25 m v offset t min to t max 45 150 25 60 25 60 m v vs. temp, average tc 0.2 1.2 0.2 0.6 0.2 0.6 m v/ c vs. supply (psrr) v s = 2 v to 18 v 110 129 110 129 114 129 db t min to t max v s = 2.5 v to 18 v 108 126 108 126 108 126 db long term stability 0.3 0.3 0.3 m v/month input bias current 1 v cm = 0 v 60 150 30 100 30 100 pa v cm = 13.5 v 80 200 50 150 50 150 pa vs. temp, average tc 0.3 0.3 0.6 pa/ c t min to t max v cm = 0 v 80 250 50 150 90 600 pa t min to t max v cm = 13.5 v 100 450 70 350 120 750 pa input offset current v cm = 0 v 40 150 30 100 30 100 pa v cm = 13.5 v 40 200 30 150 30 150 pa vs. temp, average tc 0.3 0.3 0.4 pa/ c t min to t max v cm = 0 v 80 250 50 150 80 250 pa t min to t max v cm = 13.5 v 80 450 50 350 80 450 pa frequency response unity gain crossover frequency 0.4 0.8 0.4 0.8 0.4 0.8 mhz slew rate, unity gain g = C1 0.1 0.15 0.1 0.15 0.1 0.15 v/ m s slew rate t min to t max 0.05 0.15 0.05 0.15 0.05 0.15 v/ m s input impedance differential 40 i 2 40 i 240 i 2m w i pf common mode 300 i 2 300 i 2 300 i 2g w i pf input voltage range common-mode voltage 13.5 14 13.5 14 13.5 14 v common-mode rejection ratio v cm = 13.5 v 110 132 114 132 114 132 db t min to t max 108 128 108 128 108 128 db input voltage noise 0.1 hz to 10 hz 0.5 0.5 1.0 0.5 1.0 m v p-p f = 10 hz 17 17 17 nv/ ? hz f = 1 khz 15 22 15 22 15 22 nv/ ? hz input current noise f = 10 hz 50 50 50 fa/ ? hz open-loop gain v o = 12 v r load = 10 k w 300 2000 400 2000 400 2000 v/mv t min to t max 200 1500 300 1500 300 1500 v/mv v o = 10 v r load = 2 k w 200 1000 300 1000 300 1000 v/mv t min to t max 150 1000 200 1000 200 1000 v/mv output characteristics voltage swing r load = 10 k w 13 14 13 14 13 14 v t min to t max 6 13 14 6 13 14 6 13 14 v current short circuit 15 15 15 ma capacitive load drive capability gain = +1 10,000 10,000 10,000 pf output resistance open loop 200 200 200 w power supply rated performance 15 15 15 v operating range 6 2.0 6 18 6 2.0 6 18 6 2.0 6 18 v quiescent current 380 600 380 600 380 600 m a t min to t max 400 800 400 800 400 800 m a temperature range for rated performance commercial (0 c to +70 c) ad705j ad705k industrial (C40 c to +85 c) ad705a ad705b military (C55 c to +125 c) ad705t (@ t a = +25 8 c, v cm = 0 v, and v s = 6 15 v dc, unless otherwise noted) rev. b C2C
ad705j/a ad705k/b ad705t parameter conditions min typ max min typ max min typ max units package options 8-pin cerdip (q-8) ad705aq ad705bq ad705tq 8-pin plastic mini-dip (n-8) ad705jn ad705kn 8-pin soic (r-8) ad705jr chips ad705jchips transistor count # of transistors 45 45 45 notes 1 bias current specifications are guaranteed maximum at either input. all min and max specifications are guaranteed specifications in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. specifications subject to change without notice. ad705 metalization photograph dimensions shown in inches and (mm). absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . 650 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage 3 . . . . . . . . . . . . . . . . . . . . . 0.7 v output short circuit duration . . . . . . . . . . . . . . . . indefinite storage temperature range (n, r) . . . . . . . C65 c to +125 c storage temperature range (q) . . . . . . . . . C65 c to +150 c operating temperature range ad705j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad705a/b . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c ad705t . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-pin plastic package: q ja = 165 c/watt 8-pin cerdip package: q ja = 110 c/watt 8-pin small outline package: q ja = 155 c/watt 3 the input pins of these amplifiers are protected by back-to-back diodes. if the differential voltage exceeds 0.7 v, external series protection resistors should be added to limit the input current to less than 25 ma. rev. b C3C ordering guide temperature package package model range description option ad705aq C40 c to +85 c 8-pin ceramic dip q-8 ad705bq C40 c to +85 c 8-pin ceramic dip q-8 ad705jchips 0 c to +70 c bare die ad705jn 0 c to +70 c 8-pin plastic dip n-8 ad705jr 0 c to +70 c 8-pin plastic soic r-8 ad705jr-reel 0 c to +70 c 8-pin plastic soic r-8 ad705jr-reel7 0 c to +70 c 8-pin plastic soic r-8 ad705kn 0 c to +70 c 8-pin plastic dip n-8 ad705tq C55 c to +125 c 8-pin ceramic dip q-8 ad705tq/883b C55 c to +125 c 8-pin ceramic dip q-8 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad705 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 3 2 1 4 5 6 7 8 null 8 +v s 7 v out 6 null 1 ?n 2 3 +in 5 over comp 4 ? s 0.074 (1.88) 0.0677 (1.72)
ad705Ctypical characteristics (@ +25 8 c, v s = 6 15 v, unless otherwise noted) 0 20 40 60 80 100 0 input offset voltage ?microvolts 40 ?0 ?0 +40 + 80 60 +60 +80 sample size: 610 number of units figure 1. typical distribution of input offset voltage input common mode voltage limit ?volts (referred to supply voltages) +v s ?.5 ?.0 ?.5 +1.5 +1.0 +0.5 ? s 0 5 10 15 20 supply voltage ? volts figure 4. input common-mode voltage range vs. supply voltage sample size: 85 ?5 c to +125 c 50 40 30 20 10 0 number of units ?.4 ?.2 0 +0.2 +0.4 offset voltage drift ??/ c figure 7. typical distribution of offset voltage drift 0 input bias current ?picoamperes ?20 ?0 +60 +120 200 160 120 80 40 0 number of units sample size: 1040 figure 2. typical distribution of input bias current 1k 10k 100k 1m frequency ?hz 0 10 5 15 20 25 30 35 output voltage ?volts p-p figure 5. large signal frequency response 01 2 34 5 warm-up time in minutes 4 3 2 1 0 change in offset voltage ?? figure 8. change in input offset voltage vs. warm-up time 0 40 80 120 160 200 input offset current ?picoamperes sample size: 510 ?20 ?0 0 +60 +120 number of units figure 3. typical distribution of input offset current 1k 10k 100k 1m 10m 100m source resistance ? w source resistance may be either balanced or unbalanced 100 10 1.0 0.1 offset voltage drift ??/ c figure 6. offset voltage drift vs. source resistance 60 40 20 0 ?0 ?0 ?0 ?5 ?0 ? 0 +5 +10 +15 negative i b positive i b common mode voltage ?volts input bias current ?pa figure 9. input bias current vs. common-mode voltage rev. b C4C
ad705 rev. b C5C 1000 100 10 1 voltage noise ?nv/ ? hz 1 10 100 1000 frequency ?hz figure 10. input noise voltage spectral density 0 5 10 15 20 supply voltage ? volts 500 450 400 350 300 quiescent current ?? +125 c +25 c +55 c figure 13. quiescent supply current vs. supply voltage 1 10 100 20 100k 1m 10m load resistance ?k w 24 64060 ?5 c +25 c +125 c open loop voltage gain figure 16. open loop gain vs. load resistance over temperature 1000 100 10 1 current noise ?fa/ ? hz 1 10 100 1000 frequency ?hz 10k w 100 w 20m w v out = in(2 ?10 9 w ) figure 11. input noise current spectral density 10 100 1k 10k 100k 1m frequency ?hz 1 0.1 160 140 120 100 80 60 40 20 cmrr ?db 0 figure 14. common-mode rejection vs. frequency phase gain 0 20 40 60 80 100 120 140 0.01 0.1 1 10 100 1k 10k 100k 1m 10m frequency ?hz 0 30 60 90 120 150 180 20 open loop voltage gain phase shift ?degrees figure 17. open loop gain and phase shift vs. frequency 0.5? 0510 time ?seconds figure 12. 0.1 hz to 10 hz noise voltage 180 160 140 120 100 80 60 40 20 0.1 1 10 100 1k 10k 100k 1m frequency ?hz psrr + psrr psrr ?db figure 15. power supply rejection vs. frequency output voltage limit ?volts (referred to supply voltages) +v s ?.5 ?.0 ?.5 +1.5 +1.0 +0.5 ? s 0 5 10 15 20 supply voltage ? volts figure 18. output voltage limit vs. supply voltage
ad705 rev. b C6C 0.01 0.1 1 1 10 100 1000 10,000 value of overcompensation capacitor ?pf 0.001 1k 10k 100k 1m gain bandwidth slew rate adding an external capacitor between pin 5 and ground increases the amplifier's compensation slew rate ?v/? gain bandwidth product ?hz figure 19. slew rate & gain bandwidth product vs. value of overcompensation capacitor 100 90 10 0% 20? 2v figure 21b. unity gain follower large signal pulse response r f = 10 k w , c l = 50 pf 6 4 0.1? ? s 7 0.1? +v s 2 3 ad705 r l 2.5k w c l v out v in square wave input 10k w 10k w figure 22a. unity gain inverter 1 10 100 1k 10k 100k 0.001 0.01 0.1 1 10 100 1000 frequency ?hz closed loop output impedance ? w i out = +1ma a v = +1 a v = ?000 figure 20. magnitude of closed loop output impedance vs. frequency 100 90 10 0% 5? 20mv figure 21c. unity gain follower small signal pulse response r f = 0 w , c l = 100 pf 100 90 10 0% 2v 50? figure 22b. unity gain inverter large signal pulse response c l = 50 pf 6 4 0.1? ? s 7 0.1? +v s 2 3 ad705 r l 2k w c l r f v out v in square wave input figure 21a. unity gain follower (for large signal applications, resistor r f limits the current through the input protection diodes) 100 90 10 0% 5? 20mv figure 21d. unity gain follower small signal pulse response r f = 0 w , c l = 1000 pf 100 90 10 0% 5? 20mv figure 22c. unity gain inverter small signal pulse response c l = 100 pf
ad705 rev. b C7C a high performance differential amplifier circuit figure 25 shows a high input impedance, differential amplifier circuit that features a high common-mode voltage, and which operates at low power. table i details its performance with changes in gain. to optimize the common-mode rejection of this circuit at low frequencies and dc, apply a 1 volt, 1 hz sine wave to both inputs. measuring the output with an oscilloscope, adjust trimming potentiometer r6 for minimum output. for the best cmr at higher frequencies, capacitor c2 should be replaced with a 1.5 pf to 20 pf trimmer capacitor. both the ic socket and any standoffs at the op amps input ter- minals should be made of teflon* to maintain low input current drift over temperature. *teflon is a registered trademark of e.i. dupont, co. 6 4 0.1? ? s 7 0.1? +v s 2 3 ad705 v out r2 10m w c1 5pf r3 200k w r5 * r4 * dc cmr adjust r6 500k w c2 5pf r2' 10m w r1' 100m w r1 100m w source gnd v in v in+ circuit gain, g = ? (1+ ) r2+r3 r1 r5 r4 v out = g (v in ?v in+) common mode input range = 10 (v s ?1.5v) for v s = 15v, v cm range = 135v resistors r1 and r1', r2 and r2' are victoreen mox-200 1/4 watt, 1% metal oxide. * see table i warning : potential danger from high source voltage. this differential amplifier does not provide galvanic isolation. input source must be referred to the same ground connection as this amplifier. figure 25. a high performance differentials amplifier circuit table i. typical performance of differential amplifier circuit operating at various gains circuit r4 r5 trimmed rti average circuit gain ( v )( v ) dc cmr drift tc bandwidth (db) ( m v/ 8 c) C3 db 1 1.13 k w 10 k w3 85 30 4.4 khz 10 100 w 9.76 k w3 85 30 2.8 khz 100 10.2 w 10 k w3 85 30 930 hz 100 90 10 0% 5? 20mv figure 22d. unity gain inverter small signal pulse response c, = 1000 pf 6 4 0.1? ? s 7 0.1? +v s 2 3 ad705 v out v in square wave input 10k w 5k w 10pf * 5 * response is nearly identical for capacitance values of 0 to 100pf 4.1nf figure 23a. follower connected in feed-forward mode 100 90 10 0% 5v 5? 5v input output figure 23b. follower feed-forward pulse response 6 5 8 4 1 2 3 7 ad705 overcompensation capacitor 0.1? +v s 20k w v os adjust ? s 0.1? figure 24. offset null and overcompensation connections
ad705 rev. b C8C printed in u.s.a. c1357aC2C10/94 a 1 hz, 2-pole, active filter table ii gives recommended component values for the 1 hz fil- ter of figure 26. an unusual characteristic of the ad705 is that both the input bias current and the input offset current and their drift remain low over most of the op amps rated temperature range. therefore, for most applications, there is no need to use the normal balancing resistor tied between the noninverting ter- minal of the op amp and ground. eliminating the standard bal- ancing resistor reduces board space and lowers circuit noise. however, this resistor is needed at temperatures above 110 c, because input bias current starts to change rapidly, as shown by figure 27. 6 4 0.1? ? s 7 0.1? +v s ad705 v out c1 c3 0.01? r3 2m w r2 1m w c2 r1 1m w input optional balance resistor network without the network, pins 2 and 6 of the ad705 are tied together. capacitors c1, c2 and c3 are southern electronics mpcc, polycarbonate, 5%, 50 volt. 2 3 figure 26. a 1 hz, 2-pole active filter table ii. recommended component values for the 1 hz low-pass filter desired low pole pole q c1 value c2 value pass response frequency (hz) ( m f) ( m f) bessel response 1.27 0.58 0.14 0.11 butterworth response 1.00 0.707 0.23 0.11 0.1 db chebychev 0.93 0.77 0.26 0.11 0.2 db chebychev 0.90 0.80 0.28 0.11 0.5 db chebychev 0.85 0.86 0.32 0.11 1.0 db chebychev 0.80 0.96 0.38 0.10 specified values are for a C3 db point of 1.0 hz. for other frequencies, simply scale capacitors c1 and c2 directly; i.e., for 3 hz bessel response, c1 = 0.046 m f, c2 = 0.037 m f. 90 ?0 +140 0 ?0 ?0 ?0 ?0 60 30 +120 +80 +60 +40 +100 +20 0 ?0 offset voltage of filter circuit (rti) ?? temperature ? c without optional balance resistor, r3 with optional balance resistor, r3 figure 27. v os vs. temperature of 1 hz filter 0.310 (7.87) 0.220 (5.59) 0.015 (0.38) 0.008 (0.20) 0.005 (0.13) min 0.055 (1.4) max 1 4 5 8 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.25r (0.64) 0-15 0.32 (8.13) 0.29 (7.37) pin 1 4 5 1 8 0.0500 (1.27) bsc 0.154 0.004 (3.91 0.10) 0.236 0.012 (6.00 0.20) 0.193 0.008 (4.90 0.10) 0.098 0.006 (2.49 0.23) 0.008 0.004 (0.203 0.075) 0.017 0.003 (0.42 0.07) 0.011 0.002 (0.269 0.03) 0.033 0.017 (0.83 0.43) pin 1 0.25 (6.35) 4 5 8 1 seating plane 0.100 (2.54) typ 0.31 (7.87) 0.39 (9.91) max 0.035 0.01 (0.89 0.25) 0.18 0.03 (4.57 0.76) 0.033 (0.84) nom 0.018 0.003 (0.46 0.08) 0.125 (3.18) min 0.165 0.01 (4.19 0.25) 0.30 (7.62) ref 0.011 0.003 (0.28 0.08) 0-15 outline dimensions dimensions shown in inches and (mm). cerdip (q) package plastic mini-dip (n) package 8-pin soic (r) package
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